We are looking for an RTL Design Manager to lead high-impact ASIC/SoC development
? Location: Bangalore | Hyderabad | Remote
? ? Experience: 10+ years
Role Title: SoC / Chip Lead – RTL Manager
Minimum Qualifications:
Strong expertise in Ethernet protocols and architecture.
Expertise on PCIE /Ethernet Subsystem Integration.
Experience with Verilog / SystemVerilog RTL design.
Understanding of high-speed interfaces and networking protocols.
Experience with CDC, lint, synthesis, and timing analysis.
Familiarity with AXI / AHB / APB bus protocols.
Solid debugging and problem-solving skills.
If you are interested in this position, please apply to this requisition/ mail us at
[email protected]
📌 SoC Lead (Bengaluru)
🏢 BITSILICA
📍 Bengaluru