Job Title: Senior / Lead FPGA Design & Validation Engineer
Location: India (Hybrid / Onsite)
Experience Level: 4.5 – 14 Years
Notice Period: Immediate Joiners to 15 Days Max

About the Role
We are seeking highly skilled and hands-on FPGA Design & Validation Engineers (ranging from Mid-Level to Lead) to join our high-performance Silicon & FPGA Engineering team. In this role, you will be responsible for the end-to-end architecture, RTL implementation, silicon-level validation, and deep hardware debugging of complex FPGA systems and IPs.
If you thrive in agile environments solving complex board-level, timing, and protocol challenges using advanced FPGA architectures and state-of-the-art lab/debug setups, this opportunity is for you.

Key Responsibilities
FPGA Architecture & RTL Design: Design, develop, and integrate complex IP modules and subsystems using Verilog / SystemVerilog / VHDL.
Pre-Silicon Verification & Testing: Build reusable testbenches, write targeted test cases, and perform functional verification to validate design intent prior to hardware bring-up.




Post-Silicon Hardware Validation: Drive hands-on bring-up, post-silicon validation, and lab testing of FPGA-based boards and silicon prototypes.
Deep Hardware Debugging: Diagnose and resolve complex timing closure issues, physical layer protocol failures, clock domain crossing (CDC) bugs, and board-level hardware glitches using logic analyzers, oscilloscopes, and embedded logic analyzers (e.g., ChipScope, SignalTap, Identify).
Protocol & Interface Integration: Implement and debug high-speed serial/parallel interfaces and standard protocols (e.g., PCIe, AMBA AXI/AHB/APB, Ethernet, SPI, I2C, DDR3/DDR4).
Cross-Functional Collaboration: Work closely with cross-functional teams including Board Design, Embedded Firmware, Systems Architecture, and Software to ensure seamless FW-HW integration and tape-out readiness.

Required Technical Skills & Experience
Experience: 4.5 to 14 Years in FPGA RTL Design, Emulation,

📌 FPGA (Hyderabad)
🏢 ACL Digital
📍 Hyderabad