Overview
Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional MTS Layout Design to join our MIC Design IDC team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer.
As an MTS Layout Design engineer, you’ll own the chip‑level collaterals and report directly to our layout manager in this full‑time role, joining a MIC design team dedicated to developing industry‑leading memory‑interface chips where your contributions will be instrumental to our success.
Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work.
Responsibilities
Responsible for layout design of assigned blocks with Cadence Virtuoso XL/VXL features.
Strong fundamental knowledge in layout verification checks LVS, DRC, Antenna, and Density with Calibre is a must.
Collaboration with designers to solve layout issues.
Experience in fixing various reliability issues EMIR, ESD/Latchup.
Expertise in standard layout practices such as Layout matching, parasitic, noise & noise isolation, supply consideration, latch up, shielding, Well’s substrates and Isolation.
Should have strong collaboration with Analog Designers across the globe to solve challenging problems.
Qualifications
MS Degree in Electrical/Electronic Engineering or equivalent with 5+ years of relevant experience.
Experience in layout design of Transmitter, receiver, PLL, clocking, PI, Bandgap and voltage regulators would be an added benefit.
They should have layout experience in 22nm, FINFET nodes 16nm, 12nm, 7nm.
Sound knowledge of double patterning, device matching, signal shielding, layout parasitic and layout dependent effects.
Robust fundamental knowledge in semiconductor device physics, cross-section, and construction.
📌 MTS Layout Design (India)
🏢 Rambus
📍 India