Job Details:
Job Description:
Performs functional verification of mixed signal logic components, including analog behavioral modeling, to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to mixed signal microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with digital and analog architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology.
Qualifications:
Minimum Qualifications
• Candidate must possess Bachelor's or Master's degree in Electronics, VLSI Engineering, or a related field with 4-10 years of relevant industry experience and good proficiency in verification of mixed signal IP Design.
• Candidate must be experienced in validation flow right from testbench architecture and test plan creation to verification closure, waveform debugs, functional coverage, code coverage, VCS NLP and non-NLP simulations and GLS.
• Strong knowledge of SystemVerilog and UVM methodology, experience in functional and coverage driven verification.
• Expertise in constraint-random test generation, failure root cause analysis and debugging of complex mixed signal designs.
• Capable of multitasking in agile environment with multiple teams from different geos.
• Solid verbal and written communication skills.
• Excellent debug and problem solving skills.