RTL Design Engineer- Lead (Bengaluru)

RTL Design Engineer- Lead (Bengaluru)

10 Aug
|
Einfochips
|
Bengaluru

10 Aug

Einfochips

Bengaluru

Location: Bangalore / Noida

Experience: 10-15 Years

Notice Period: Open to all notice periods

Robust experience in RTL Design / ASIC / SoC Design

Hands-on expertise in Verilog / SystemVerilog / VHDL

Experience in micro-architecture development, RTL coding, and design integration

Strong understanding of SoC architecture and industry-standard protocols such as AXI, AHB, APB, PCIe, USB, etc.

Experience in timing closure, synthesis, and low-power design concepts

Ability to lead design teams and drive end-to-end project execution

Strong debugging and problem-solving skills

Excellent stakeholder management and communication skills

📌 RTL Design Engineer- Lead (Bengaluru)
🏢 Einfochips
📍 Bengaluru

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