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Experience: 4+ yrs
Location: Bengaluru
Job Type: Full-time
We are seeking talented Physical Design Engineers to contribute to the implementation of high-performance ASIC and SoC designs across advanced semiconductor technology nodes. This role is ideal for professionals with robust expertise in Cadence physical design tools and Floorplanning, along with a passion for delivering optimized silicon solutions that meet aggressive power, performance, and area (PPA) goals.
As a Physical Design Engineer, you will work closely with RTL, Design Verification, DFT, STA, and Foundry teams throughout the complete physical implementation cycle. You will be responsible for developing efficient floorplans, driving timing closure, resolving implementation challenges, and ensuring successful tape-outs. This position offers the opportunity to work on cutting-edge semiconductor products while contributing to advanced implementation methodologies and continuous process improvements.




Key Responsibilities
Execute end-to-end physical design implementation from synthesized netlist through GDSII for ASIC and SoC projects.
Develop and optimize floorplanning strategies to achieve target PPA while minimizing congestion and improving routability.
Perform placement, clock tree synthesis (CTS), routing, timing optimization, and physical verification using Cadence implementation tools.
Collaborate with RTL, DFT, STA, and Verification teams to resolve design issues and support successful physical implementation.
Drive timing closure by resolving setup, hold, signal integrity, IR drop, electromigration, and congestion-related challenges.
Support engineering change orders (ECOs), implementation updates, and design optimization throughout the project lifecycle.
Perform design quality checks, physical verification, and signoff activities to ensure compliance with foundry and manufacturing requirements.

📌 Physical Design engineers (Bengaluru)
🏢 Weekday AI
📍 Bengaluru