ACL Digital is looking for a proactive Functional Verification Engineer to join our team in Hyderabad If you have hands-on experience coding in SystemVerilog/UVM and a robust track record of developing block- or IP-level testbenches (subsystem/SoC level is a plus), we want to hear from you. We need an independent self-starter who communicates effectively and reliably meets project schedules. If you are ready to make an impact and have a notice period of 0 to 30 days, send your CV today