Engineering Group, Engineering Group > Hardware Engineering
General Summary:
Job Overview
Candidate will be responsible for next generation WLAN hardmacro implementation
The candidate will work with best-in-class methodologies, tools and technology to design creative WLAN products at the block/IP-level and at system-level in 6nm and beyond (process technologies).
This role will require the candidate to work on physical and power aware synthesis, logic equivalence, constraints generation & validation, static timing analysis
Optimize data path design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
You will be working with physical design team (and other teams) on timing closure, CAD teams, IP teams and Design Technology Teams for flow scripts/tools development and validation.
Should be able to work on netlist level ECOs manually or with conformal ECO tool.
The candidate should also possess automation skills and be well versed in scripting languages
The candidate should be able to mentor junior members of the team.
Minimum Qualifications:
Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Minimum Qualifications
Bachelor’s or Master’s in Electrical Engineering or related field
8 years of experience in SOC logic synthesis and timing constraints
Preferred Qualifications
Must hold a Bachelor’s and/or a Master’s in Electrical Engineering with at least 8+ years’ experience in SOC logic synthesis and