Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D; capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You Are
You have spent years in RTL design knowing that clean code at the front end saves weeks of pain downstream. You have learned the hard way that a missed clock domain crossing or an unchecked reset scheme does not just slow synthesis, it breaks trust with the implementation team counting on your work. You think in terms of signoff quality before tape-out pressure hits, not after.
You are the engineer who opens Spyglass before the design review, not during integration panic. When you see a CDC violation, you do not just waive it,
you trace it back to the architecture decision that caused it and you ask whether that decision still makes sense. You have written SDC constraints that actually reflect design intent, not just pass a tool check.
Working across subsystems and full SOCs does not intimidate you. You have integrated third-party IP, debugged synthesis mismatches at 2 a.m., and run formality enough times to know when the issue is in the script versus the RTL. You care about the quality of what you hand off because you have been on the receiving end of messy handoffs before.
At Synopsys, you will work on real customer SOC projects that ship into production, alongside a team that takes signoff seriously.
What You'll Be Doing
Run RTL quality signoff using Spyglass for LINT, CDC, and RDC checks across IP blocks, subsystems, and full SOC designs
Develop and validate timing constraints in SDC format for synthesis and static timing analysis, ensuring design intent is captur