? Hiring: Full-Chip STA Engineer

We are looking for an experienced Full-Chip STA Engineer to join our VLSI team.
? Location: Bengaluru
? Experience: 5+ Years
⏳ Notice Period: Immediate to 30 Days Preferred

Key Responsibilities:
Perform Full-Chip Static Timing Analysis (STA) and timing sign-off.
Develop and validate SDC constraints.
Debug setup, hold, recovery, and removal timing violations.
Perform timing closure across MMMC scenarios.
Generate and validate timing ECOs.
Work closely with RTL, Synthesis, Physical Design, and DFT teams.
Support tape-out and sign-off activities.

Required Skills:
Robust experience in Full-Chip STA and timing sign-off.
Hands-on experience with PrimeTime (PT/PT-SI) or Cadence Tempus.
Expertise in MMMC, SDC, Timing Closure, and ECO Flow.
Knowledge of advanced technology nodes (16nm/7nm/5nm preferred).
TCL scripting skills.

? Qualification: B.E./B.Tech/M.E./M.Tech in ECE, EE, VLSI, or a related field.

📌 STA Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru