Principal Engineer – DFT (Design for Test)

Location: Bengaluru, India

Experience: 12–18 Years

About the Role

We are seeking a Principal Engineer – DFT to lead the architecture, implementation, and signoff of Design-for-Test solutions for complex, high-performance SoCs. You will drive end-to-end DFT strategy, collaborate with Architecture, RTL, Physical Design, and ATPG teams, and ensure high test quality, manufacturability, and first-pass silicon success across advanced technology nodes.

Key Responsibilities

- Define and drive the DFT architecture for complex SoCs from specification to silicon.
- Own end-to-end DFT implementation , including Scan Insertion, Scan Compression, MBIST, LBIST, JTAG (IEEE 1149.1/1500), Boundary Scan, and TAP Controller integration.
- Develop and validate DFT specifications, test modes, and test access mechanisms.
- Generate and optimize ATPG patterns for stuck-at, transition, path-delay, bridge, and cell-aware fault models.
- Drive test coverage closure , pattern optimization, diagnosis, and silicon bring-up support.
- Collaborate with Physical Design teams on scan chain reordering, DFT-aware timing closure, and DRC cleanup.
- Work closely with RTL and Verification teams to ensure DFT functionality through simulation and formal verification.
- Develop DFT automation flows and improve methodology using Tcl, Python, or Perl.




- Mentor engineers and provide technical leadership across DFT execution.

Required Qualifications

- 12–18 years of hands-on experience in Design for Test (DFT) for complex ASIC/SoC designs.
- Strong expertise in Scan Insertion, Scan Compression, ATPG, MBIST, LBIST, JTAG/TAP Controller, and Boundary Scan .
- Extensive experience with Mentor Tessent or equivalent DFT tool suite.
- Solid knowledge of fault models , test coverage analysis , pattern generation , and diagnosis .
- Good understanding of Physical Design , STA , scan timing, and DFT signoff.
- Experience with advanced technology nodes ( 7nm/5nm/3nm ) is highly preferred.
- Proficiency in Tcl, Python, or Perl for automation and flow development.

Preferred Qualifications

- Experience with IEEE 1687 (IJTAG) and advanced DFT methodologies.
- Knowledge of low-power DFT, compression architectures, and memory repair (BISR/BIRA).
- Exposure to silicon bring-up, production test, and yield improvement.
- Strong understanding of ARM-based SoCs and complex multi-core architectures.

Why Join Us? Be part of a world-class silicon engineering team building next-generation AI, HPC, Automotive, Networking, and Data Center SoCs. You'll define DFT architecture, influence test strategy, and help deliver high-quality silicon at scale while solving some of the industry's most complex test challenges.

📌 Principal Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru