Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantag

- eThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, cutting-edge, and to make an impact
- .Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees
- .The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer succes
- sMultiple avenues of learning and development available for employees to explore as per their specific requirement and interest

sYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every da

**y

Location: Hyderabad/PUNE/NOI**

DA

Job Descrip tionRole Sum maryWe are looking for an experien ced Principal Analog Design Engi neer to drive the design and delivery of high‑speed interface IPs, with a strong emphasis on Die‑to‑Die (D2D)



interconnects based on the UCIe stan dard and advanced package technolo gies. The role requires hands‑on ownership f rom architecture through silicon brin g‑up, working closely with layout, verification, package, and system te

**ams.

Key Responsibil**

- itiesArchitect, design, and del iver high‑speed analog / mixed‑signal cir cuits for Die‑to‑Die and chiplet‑based systems, including UCIe‑compliant interf
- aces.Own analog blocks for high‑speed inter faces such as clocking, TX/RX front‑ends, termination schemes, biasing, and equalization support circ
- uits.D rive architecture defin ition, feasibility analysis, and design trade‑offs considering signal integrity, power, noise, and packaging parasi
- tics.Per form schematic design, simulation, and optimiz ation across PVT corners using industry‑standard EDA t
- ools.Work closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co‑optimize circuit and package de
- sign.Sup port layout re views, parasitic extraction analysis, and post‑layout sign‑off for high‑speed perform
- ance.Collaborate with AMS verific ation, digital, and system teams to enable full‑chip integration and valida
- tion.Participat e in silicon bring‑up, debug, and characteriz ation, including correlation with simulation res




- ults.Contribut e to design methodology, checklists, and best prac tices for high‑speed analog and D2D des

**igns.

Required Qualific**

- ationsBachelor’s or Master’s degr ee in Electrical / Electronics Engin eering or related
- field.8+ years of hands‑on experien ce in analog / mixed‑signal IC d
- esign.Strong experience with high‑speed interface design (e.g., DDR, PCIe, SerDes, Die‑to‑Die l
- inks).Solid understandi ng of UCIe standard co ncepts, D2D PHY requirements, and chiplet architec
- tures.Experience working with advanced packaging techno logies and understanding package‑induced effects on high‑speed sign
- aling.Proficien cy in schematic‑level design, simulation, and debug across PVT co
- rners.Strong fundamenta ls in analog circuit theory, signal integrity, noise analysis, and clo

**cking.

Preferred / Nice‑to‑Have**

- SkillsDirect hands‑on experienc e with UCIe PHY design or inte g
- ration.Expos ure to AMS verificatio n flows and mixed‑signal simulation enviro
- nments.Experienc e with post‑silico n debug and corre
- lation.Knowle dge of power integrity, thermal conside rations, and package‑aware design
- flows.Ability to mentor junior engineers and lead technical discu

**ssions.

What Success Lo**

- oks LikeRobust, s calable UCIe / D2D an alog IPs meeting performance, power, and reliability
- targets.Smooth collaboration across design, verification, and p ackagin
- g teams.Predictable execution align ed with project milestones and KPI s
- / OKRs.Strong ownership minds et from architecture to

silicon.

📌 Principal Analog design Engineer (Hyderabad)
🏢 Cadence
📍 Hyderabad