We are looking for hands‑on experienced “on contract Engineers” to work on ZEBU Emulation, validate PCIe/LPDDR/ONFI Controller + IPs and SoC integrations across pre‑silicon phases and specializes. The knowledge of HANDS ON – ZEBU Prototyping platform is positive to have.
You’ll be part of – pre silicon activities with various interfaces like LPDDR, ONFI, PCIe etc along with – existing prototyping team on ZEBU systems.
You will be responsible for PCIE, LPDDR implementation on ZEBU platforms.
The is contract role which involves deep knowledge of either of specifications like ONFI, LPDDR, PCIe (Gen3/4/5/6) and SOC validation methodologies across pre-silicon phases.
Candidate must posses ‘hands on knowledge’ of ZEBU Emulation flow, transactors, Synopsys Protocompiler Flow, Xilinx Ultrascale and higher devices, Vivado flow, SERDES configuration for PCIE G2/4/6 etc
Job Responsibilities At Glance
Complete HANDS On Xilinx FPGA Flow, Vivado Flow,
ZEBU flow and Protocompiler Tool flow is Must to Have
Overall ownership of complete SOC deployment on Pre Silicon platforms like ZEBU
Work with overseas teams for PCIe/LP bring-up/debug
Should be writing the Verilog RTL when required, should be able to debug using Xilinx FPGA Vivado Flow
Proficiency In FPGA Debug Skills
Must be HANDS on Xilinx FPGA debug using Chipscope flow
Strong root-cause skills across hardware, RTL layers
Pre-Silicon Validation Activities
Should be part of the Prototyping and Emulation team to get the best possible PCIe/LPDDR/ONFI version validated for given SOC
Should be part of the team interacting with Xilinx/SNPS teams for PCIe/LPDDR Implementation/Debug on FPGA’s along with Prototyping Teams
Should be able to debug, use PA’s and get the PCIe/LPDDR/ONFI end to end set up working
Should be part of the team with SOC C, FW/AE to make sure the PCIE validation is stable on prototyping/emulation platforms
Provide debug logs