Job Details:
Job Description:
Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to microarchitecture specifications.
Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.
Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams.
Maintains and improves existing functional verification infrastructure and methodology.
Participates in the definition of verification infrastructure and related TFMs needed for functional design verification.
Qualifications:
Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Bachelor's Degree with 3-7 years of experience.
Minimum Qualifications:
1. Very good perl, python (or) any programming language.
2. Excellent in system Verilog
3. Very valuable in computer architecture.
4. Exposure to AMBA protocols preferred.
Preferred Qualifications:
• Bringing up coherent protocols from 0 to1.
• 1 years of Experience on Network on Chip verification.
• 1 years of experience developing protocol checkers, bridge checkers, VIP integration,
• Configurable IP verification.
• Strong in coherency architecture and experience on Coherent Protocols CHI
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job Type:
Experienc