Project Role : Design-For-Test (DFT) Engineer
Project Role Description : Enable effective post-manufacturing chip testing by integrating testability features during the design phase. Apply DFT methodologies such as scan chains, Built-In Self-Test (BIST), and boundary scan to detect defects and enhance test coverage. Ensure high-quality silicon by collaborating with design and verification teams to optimize for test efficiency and fault isolation.
Must have skills : Design for Testability (DFT)
Good to have skills : NA
Minimum 3 year(s) of experience is required
Educational Qualification : 15 years full time education
Summary:
As a Design-For-Test Engineer, a typical day involves embedding testability features into chip designs to facilitate effective testing after manufacturing. This role requires close collaboration with design and verification teams to ensure that the integrated test mechanisms effectively identify defects and improve overall test coverage. The engineer focuses on optimizing the design to support fault isolation and enhance the quality of the silicon product,
ensuring that the final output meets rigorous standards for reliability and performance.
Roles & Responsibilities:
- Expected to perform independently and become an SME.
- Required active participation/contribution in team discussions.
- Contribute in providing solutions to work related problems.
- Collaborate with cross-functional teams to integrate test features seamlessly into design workflows.
- Analyze test results and provide feedback to improve design for enhanced testability.
- Support junior team members by sharing knowledge and assisting in problem-solving.
- Continuously update and refine test methodologies to keep pace with evolving design challenges.
Professional & Technical Skills:
- Must To Have Skills: Proficiency in Design for Testability (DFT).
- Experience with scan chain insertion and optimization techniques.
- Familiarity with Built-In Self-Test (BIST) architectures an