Job Details:
Job Description:
Altera is looking for a talented and driven Design Verification Engineer to Designs, develops, validates, and/or debugs software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.
Key Responsibilities:
Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
Develop verification components, including drivers, monitors, scoreboards, and checkers.
Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.




Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.
Qualifications:
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field .
2+ years of experience in ASIC or FPGA design verification.
Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
Strong hands-on experience in developing UVM-based testbenches and verification components.
Proficiency in contemporary verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
Familiarity with

📌 Design Verification Engineer (Madhapur)
🏢 Altera
📍 Madhapur