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Experience: 4+ yrs
Location: Bengaluru
Job Type: Full time
We are seeking a highly skilled Senior IO Design Engineer to contribute to the design and implementation of advanced SoC IO architectures. This role is ideal for engineers with strong expertise in pad ring planning, IO implementation, bump map definition, and physical design handoff. You will work closely with cross-functional engineering teams to develop robust, high-performance IO solutions that meet product, packaging, and silicon requirements.
As a Senior IO Design Engineer, you will play a critical role in defining IO connectivity, optimizing pad ring layouts, supporting package integration, and ensuring seamless collaboration across architecture, physical design, verification, and validation teams. This position offers the opportunity to work on cutting-edge semiconductor technologies and complex SoC development programs.
Key Responsibilities
Plan, design, and optimize pad rings, bump maps,



and package substrate layouts for advanced SoC designs.
Develop and maintain IO connectivity, pad ring definitions, and bump pattern implementations.
Generate and validate physical design handoff deliverables, including pad ring DEF files, Verilog netlists, and related implementation data.
Collaborate with architecture, physical design, package engineering, technology, and foundry teams throughout the development lifecycle.
Support verification, emulation, ASIC validation, and silicon debug activities by analyzing IO-related issues and implementing design improvements.
Optimize IO placement, connectivity, and implementation to meet performance, manufacturability, and packaging requirements.
Ensure compliance with IO design standards, package constraints, and implementation best practices.
Participate in design reviews, technical discussions, and cross-functional planning sessions.
Develop automation scripts and imp

📌 Senior IO Design Engineer (Bengaluru)
🏢 Weekday AI
📍 Bengaluru