Role Overview
We are seeking an experienced RTL Design Engineer with 5–15 years of hands-on experience in digital design and IP development. The ideal candidate will have strong expertise in RTL architecture and micro-architecture definition, with experience developing reusable IP for SoC integration.
Exposure to wireless systems (preferably Wi-Fi) and communication/peripheral IP such as SPI, UART, I2C, DMA, etc., is highly desirable.
Key Responsibilities
Develop high-quality, synthesizable RTL (Verilog/SystemVerilog) for digital IP blocks.
Drive IP development from specification to tape-out.
Ensure designs meet performance, power, and area (PPA) targets.
Develop and maintain design documentation (micro-architecture spec, design spec, integration guide).
Collaborate with verification teams to develop test plans and debug functional issues.
Support synthesis, lint, CDC/RDC, and timing closure activities.
Work closely with SoC integration teams for IP integration and bring-up.
Support post-silicon validation and debug.
Contribute to IP reuse, configurability,
and design methodology improvements.
Mentor junior engineers
Required Qualifications
Bachelor’s or Master’s degree in Electronics/Electrical Engineering or related field.
5–15 years of experience in RTL design and digital IP development.
Robust proficiency in Verilog/SystemVerilog.
Solid understanding of:
Digital design fundamentals
FSM and datapath design
Pipelining and performance optimization
Clock domain crossing (CDC) and reset domain crossing (RDC)
Low-power design concepts
Experience with synthesis and timing analysis.
Strong RTL and gate-level debugging skills.
Familiarity with industry-standard EDA tools (Synopsys/Cadence/Mentor).
Experience with AMBA protocols (AXI/AHB/APB).
Preferred Experience
Experience developing communication or peripheral IP such as:
SPI, UART, I2C/I3C
DMA controllers
Timers, interrupt controllers
Memory controllers
Exposure to wireless subsystems, preferably Wi-Fi (IEEE 802.11)