Role Overview Drive pre-silicon validation strategy and emulation infrastructure for a complex SoC featuring ARM and/or RISC-V cores with high-speed PCIe-class interfaces, using Cadence Palladium Z2/ZX platforms.
Key Responsibilities
Architect and own the end-to-end emulation setting on Cadence Palladium Z2/ZX for a multi-core SoC (ARM Cortex / RISC-V)
Define emulation bring-up strategy including partitioning, compile flows, and debug methodology across multi-million gate designs
Design and integrate PCIe-like interface models (TLM/BFM/synthesizable) for emulation — covering link training, transaction layer, and data path stimulus
Build and maintain ICE (In-Circuit Emulation) connectors and co-emulation bridges to real PCIe host systems, FPGAs, or target boards
Develop emulation-specific IP including speed adapters, FIFO bridges, and clock domain crossing helpers to overcome emulation clock frequency limitations
Define and enforce compile-time and runtime debug strategies: waveform probing,
transaction logging, assertion coverage on Palladium
Collaborate with RTL designers, firmware engineers, and verification leads to map SoC subsystems (CPU, interconnect, PHY, memory controllers) onto the emulation platform
Establish software co-development flows: boot bare-metal and OS images (Linux/RTOS) on emulated ARM/RISC-V cores, enabling early firmware and driver validation
Manage emulation farm scheduling, utilization, and regression infrastructure — integrating with LSF/grid job management
Drive emulation-to-silicon correlation analysis and document discrepancies
Own design partitioning for hybrid emulation/simulation (Palladium + VCS/Xcelium mixed-signal co-sim)
Champion reuse of verification IP (VIP) — particularly PCIe, AXI, CHI — across simulation and emulation environments
Required Skills & Experience
8+ years in ASIC/SoC verification with 4+ years hands-on Palladium (Z1/Z