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SMTS SILICON DESIGN ENGINEER
Lead SOC Verification Engineer
AMD is seeking a highly experienced SMTS Design Verification Engineer to lead verification efforts for next-generation chiplet SoC designs. The ideal candidate will possess deep expertise in developing scalable testbenches using SystemVerilog and UVM,
demonstrate strong proficiency in formal and assertion-based verification methodologies, and have a understanding of RTL integration.
Key Responsibilities
Lead the development and execution of scalable, reusable SystemVerilog/UVM testbenches for server-class SoC verification.
Drive verification strategy and planning for complex server SoC architectures, including integration of high-speed interfaces and subsystems.
Develop and deploy SystemVerilog Assertions (SVA) for assertion-based verification, ensuring protocol and interface correctness across SoC boundaries.
Apply formal verification techniques, including property checking and formal exploration, to critical SoC blocks.
Collaborate with cross-functional teams (RTL, DFT, validation, firmware, and physical design) to resolve complex design and verification challenges in server SoC environments.
Lead coverage analysis and closure, including functional, code, and formal coverage metric
📌 Chiplet Verification Lead (Bengaluru)
🏢 AMD
📍 Bengaluru