Senior Principal Engineer / Senior Manager – SoC / Chip Lead
Memory Interface Division (MID)
Experience
20+ Years
Location
US / Bangalore
About the Role
We are seeking a highly accomplished Senior Principal Engineer / Senior Manager – Chip Lead to drive the development and execution of next-generation high-performance SoC products. This role will provide end-to-end technical leadership spanning architecture definition, SoC integration, execution planning, silicon realization, and product bring-up.
The ideal candidate will have a solid track record of leading complex, advanced-node SoCs from concept through production, with deep expertise in large-scale digital integration, high-speed interfaces, and cross-functional execution. The role requires close collaboration with architecture, design, verification, physical design, DFT, firmware, package, analog, and product engineering teams to ensure successful delivery of world-class silicon products.

Key Responsibilities




Own end-to-end technical leadership and execution of complex SoC programs from architecture through silicon production.
Drive l, integration strategy, execution schedules, risk management, and tape-out readiness.
Lead cross-functional teams across digital design, verification, physical design, DFT, firmware, validation, packaging, and product engineering.
Define chip-level architecture, integration requirements, performance targets, and power/area objectives.
Drive technical decision-making and trade-off analysis across architecture, implementation, and product requirements.
Oversee subsystem and IP integration, ensuring successful deployment of complex multi-domain SoCs.
Partner with analog and SerDes teams to integrate high-speed interfaces and mixed-signal subsystems into the overall chip architecture.
Lead design reviews, execution reviews, silicon readiness assessments, and post-silicon debug activities.
Drive issue resolution across the development lifecycle and ensure successful first-pass silicon

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