Senior STA Engineer (Bengaluru)

Senior STA Engineer (Bengaluru)

10 Aug
|
Leadsoc Technologies
|
Bengaluru

10 Aug

Leadsoc Technologies

Bengaluru

Senior Full-Chip STA Engineer
Experience: 7–10 Years
Location: Bengaluru, India
Role
We are looking for a Senior Full-Chip Static Timing Analysis (STA) Engineer to own timing signoff and closure for large, high-performance SoCs across advanced technology nodes. You will be responsible for driving full-chip timing convergence from post-CTS through tapeout, partnering with Physical Design, RTL, DFT, Synthesis, Library, and CAD teams to achieve first-pass silicon success.
Responsibilities
Own full-chip STA signoff across all functional modes, PVT corners, and MCMM scenarios.
Drive timing closure for setup, hold, recovery, removal, minimum pulse width, clock gating, and asynchronous timing checks.
Perform advanced timing analysis using OCV, AOCV, POCV, LVF, CRPR, and variation-aware signoff methodologies.
Lead full-chip timing convergence by analysing critical timing paths and driving closure with PD, RTL, and Architecture teams.
Debug complex timing issues related to clock architecture, long interconnects, hierarchical interfaces, timing exceptions, and generated clocks.




Perform Signal Integrity (SI), Crosstalk, Noise, and Delta Delay analysis and drive clean timing signoff.
Develop, validate, and maintain SDC constraints, ensuring complete timing coverage across the chip.
Execute and validate timing ECOs while balancing performance, power, and area (PPA).
Correlate timing across Synthesis, Place & Route, and Signoff environments to ensure silicon accuracy.
Drive hierarchical and top-level timing integration, interface timing closure, and partition-level signoff.
Work closely with Physical Design teams during CTS, routing, post-route optimization, and final signoff.
Develop automation using Tcl, Python, or Perl to improve signoff productivity, regression, QoR analysis, and reporting.
Support tapeout readiness through comprehensive timing signoff reviews and cross-functional design closure.
Required Qualifications
B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engin

📌 Senior STA Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru

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