Senior Engineer – Static Timing Analysis (India)

Senior Engineer – Static Timing Analysis (India)

10 Aug
|
tylsemi
|
India

10 Aug

tylsemi

India

Role Overview

We are seeking a highly skilled Senior Engineer – Static Timing Analysis (STA) to join the Physical Design team. In this role, you will be responsible for driving timing closure and signoff activities for complex SoC designs across advanced technology nodes. You will collaborate with synthesis, place-and-route, CTS, and ECO teams to ensure robust timing convergence and successful tapeout delivery. The ideal candidate should possess strong STA fundamentals, signoff expertise, and hands-on experience with industry-standard timing tools.

What You’ll Do

Perform block-level and full-chip Static Timing Analysis for setup, hold, recovery, removal, and noise checks
Drive timing closure by debugging and resolving timing violations across multiple modes and corners
Develop and validate timing constraints including SDC generation and timing exception management
Work closely with synthesis, CTS, P&R;, and ECO teams to optimize timing, area, and power
Execute MMMC timing analysis using industry-standard STA methodologies




Perform ECO implementation and timing signoff for advanced-node designs
Support tapeout activities and ensure clean timing signoff delivery

What We’re Looking For

Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or VLSI-related discipline
5+ years of experience in STA, timing closure, or Physical Design signoff roles
Solid understanding of STA concepts including setup/hold analysis, clock skew, jitter, and timing exceptions
Hands-on experience with Synopsys PrimeTime and timing signoff methodologies
Good understanding of synthesis, CTS, place-and-route, and ECO flows
Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement

Good to Have

Experience with advanced nodes such as 7nm, 5nm, or below
Exposure to low-power methodologies including UPF/CPF and power-aware STA
Knowledge of SI/noise analysis, OCV/AOCV/POCV methodologies, and timing convergence techniques

Success in This Role Looks Lik

📌 Senior Engineer – Static Timing Analysis (India)
🏢 tylsemi
📍 India

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