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Job Description:
Role Overview
You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.
Key Responsibilities
Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
Define verification plans, design testbenches, and create directed and constrained-random testcases.
Write and debug testcases and sequences for DDR prot

📌 Principal Engineer-Verification (Bengaluru)
🏢 Microchip Technology
📍 Bengaluru