WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build excellent products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

? THE ROLE

As a PHY‑V Lead, you will own physical verification sign-off, full-chip integration, and packaging interface (RDL) planning for advanced SoC programs. You will drive DRC/LVS clean tapeouts, integration quality, and sign-off predictability across complex multi-IP designs.

This role requires strong expertise in physical verification, top-level integration,



and advanced packaging alignment, along with the ability to lead cross-functional execution across PD, Analog, and Packaging teams.

? THE PERSON

Strong technical leader with deep PD + Physical Verification understanding
Proven ownership of sign-off closure for complex SoCs
Ability to drive execution across multiple teams and dependencies
Detail-oriented with focus on quality, manufacturability, and schedule predictability
Comfortable operating in high-pressure tapeout environments

? Key Responsibilities

✅ Physical Verification & Sign-off Ownership

Drive end-to-end DRC, LVS, ERC, antenna closure at block and full-chip level
Define and enforce sign-off methodology and quality criteria
Own foundry rule decks, waivers, and risk assessments
Deliver sign-off clean GDS for tapeout

✅ SoC / Full-Chip Integration

Lead top-level integration of IPs/macros into SoC
Own:
GDS assembly
Hierar

📌 PHY V (Bengaluru)
🏢 AMD
📍 Bengaluru