Experience: 5+ Years
Location: Bengaluru (Preferred)
Notice Period: Immediate to 30 Days Preferred
Job Description
We are looking for an experienced Physical Design Engineer with 5+ years of hands-on experience in full-chip or block-level physical implementation. The ideal candidate should have expertise in advanced technology nodes, timing closure, and physical design sign-off while working on complex SoC designs.
Key Responsibilities
Perform end-to-end Physical Design implementation from Netlist to GDSII.
Handle Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
Achieve timing closure across all MMMC scenarios.
Perform congestion analysis, optimization, and routing closure.
Optimize designs for Power, Performance, and Area (PPA).
Work on Signal Integrity (SI), Crosstalk, IR Drop, and Electromigration (EM) analysis and closure.
Perform ECO implementation for timing and functional fixes.
Analyze and resolve DRC, LVS, and Antenna violations.
Collaborate with RTL, Synthesis, DFT, STA,
and Verification teams to resolve implementation issues.
Support physical design sign-off activities and tape-out.
Required Skills
Solid understanding of the complete Physical Design flow.
Hands-on experience in:
Floorplanning
Power Planning
Placement & Optimization
Clock Tree Synthesis (CTS)
Routing
Timing Closure
Physical Verification (DRC/LVS)
ECO Implementation
MMMC Setup & Analysis
Signal Integrity (SI)
IR Drop & EM Analysis
Experience with advanced technology nodes (16nm/7nm/5nm/3nm is preferred).
Strong debugging and problem-solving skills.
Preferred Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
Experience with block-level and full-chip implementation.
Strong u