ADVANCE YOUR CAREER. ADVANCE THE WORLD.
At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.
AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.
Key Responsibilities
Lead IR/EM (Static IR, Energetic IR, Power EM and Signal EM) analysis and signoff activities for complex SoC/IP designs from floorplan stage through tapeout.
Own power integrity closure by driving IR-drop, electromigration, rush current, power-grid and power-delivery-network (PDN) optimization across multiple design stages.
Collaborate with Physical Design, STA, Power Architecture, Package, Library and Full-Chip teams to achieve robust power integrity signoff.
Perform early power-grid analysis, bump planning validation, power-domain verification, and design reviews to ensure signoff readiness.
Analyze EMIR violations, determine root causes, define corrective actions, and drive ECO implementation and verification.
Develop methodologies, automation, and flows for power integrity analysis, debug, reporting, and closure.
Work closely with CAD teams and EDA vendors to improve EMIR signoff efficiency, accuracy, runtime, and scalability.
Provide technical leadership and mentoring for engineers on power integrity concepts, EMIR closure methodologies, and best practices.
Drive project planning, execution, risk assessment, and convergence tracking for IR/EM signoff milestones.
Support Full-Chip signoff including power delivery analysis, TSV/uBump coverag
📌 VSI and FC Lead (Bengaluru)
🏢 AMD
📍 Bengaluru