Semiconductors are becoming the foundation of every major technological leap — from AI to energy to autonomy. The chip design community is standing at a rare inflection point, where decades of incremental progress are giving way to a current era shaped by AI-native workflows, open ecosystems, and open-source EDA which has matured into a powerful force across simulation, logic synthesis, physical design, and verification.
But the next wave of exponential productivity acceleration won't come from isolated tools. It will come from end-to-end, AI-first design systems that learn your flow, protect your IP, scale with your team, and continuously accelerate the path from idea to silicon. That belief is the North Star behind CaretEDA.
We are an Agentic-first organization and full believers in bringing the power of agentic AI to EDA. We are 100% hands-on. And we measure success in the only way that matters:
how many customers we make successful.
About The Role
CaretEDA is seeking Senior Hardware Design & Verification Engineers in Bengaluru who will work directly with customers adopting our Spec-to-Netlist™ AI-native design platform.
This role blends deep technical understanding (RTL, simulation, chip development) with customer-facing clarity, helping engineering teams integrate, validate, and scale AI-assisted design workflows inside their existing environments.
You will collaborate with global engineering, product, and customer teams to ensure smooth deployments, build reproducible debug scenarios, and help customers get the most out of CaretEDA's multi-agent, AI-driven design flows.
Key Responsibilities
Customer Deployment & Technical Guidance
Work closely with customer design and DV teams to integrate Spec-to-Netlist™ into their existing flows.
Understand customer architecture specs, RTL conventions, verifi