About The Opportunity

A fast-scaling engineering services firm in the Semiconductor & Electronics Design Verification sector, we partner with global chipmakers to validate complex SoC, IP, and RTL designs at scale. Our team builds next-gen verification environments using cutting-edge methodologies and automation to deliver silicon with zero escapes—helping clients de-risk tapeouts and accelerate time-to-market.

Role & Responsibilities

Should have atleast 10 Years of relevant experience in DV and have handled a team size of atleast 10 members.
Lead end-to-end design verification for complex digital IPs and SoCs—from testbench architecture to coverage closure and regression management.
Architect and implement scalable UVM-based verification environments with constrained-random stimulus, functional coverage, and scoreboard logic.
Define and enforce verification sign-off criteria, including code coverage, functional coverage, and assertion coverage metrics across multiple design blocks.
Mentor junior engineers on UVM best practices, debug methodologies,



and verification productivity tools; drive team-wide adoption of reusable verification IP (VIP).
Collaborate with design and DFT teams to align verification strategy with testability, clock domains, and power intent; ensure coverage of corner cases and failure modes.
Automate regression flows using Python/Makefiles/Shell scripts; integrate CI/CD pipelines with Jenkins or equivalent tooling for nightly regression and gating checks.

Skills & Qualifications

Must-Have

UVM
SystemVerilog
Verilog
Functional Coverage
SV Assertions (SVA)
Makefile
Python
Jenkins

Preferred

Formal Verification ( JasperGold / Questa Formal )
Verification IP (VIP) development
EDA Tools (VCS, Xcelium, Questa)

Perks & Culture Highlights

Comprehensive Health & Wellness: Full medical, dental, and vision insurance coverage; mental health support via telehealth platforms; wellness stipends and annual health check-ups.
Financial Security: Compet

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