Formal verification engineerST RM 4299) (Hyderabad)

Formal verification engineerST RM 4299) (Hyderabad)

10 Aug
|
Source right
|
Hyderabad

10 Aug

Source right

Hyderabad

Position: Formal verification engineer (IRT40ST RM 4299)

- Experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification).

- Experience with programming languages (e.g., Python/Perl and TCL).

- Experience with at least one formal verification tool (e.g., Cadence Jasper, Synopsys VC-Formal).

- Expertise in property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL.

📌 Formal verification engineerST RM 4299) (Hyderabad)
🏢 Source right
📍 Hyderabad

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