We are hiring for one of our reputed clients for the following position. If you're interested and your experience matches the requirement, we'd love to hear from you.
Title:ASIC /RTL Design Engineer 3
Location: Bangalore
Duration: 12 Months
Key Skills:
- Strong hands-on experience in Verilog/SystemVerilog and UVM
- Experience in functional verification, testbench development, and debugging
- Knowledge of AMBA protocols (AXI/AHB/APB)
- Valuable understanding of digital design fundamentals
- Exposure to ARM-based SoCs is an added advantage
- Scripting experience in Perl, TCL, Shell, or Make