Role & responsibilities
Requirements generation and RTL design using VHDL
Robust understanding of the DO-254 development lifecycle
FPGA design, synthesis, timing analysis, and design constraints
Exposure to Xilinx/Altera FPGA architectures
Experience with PCIe, ARINC, Ethernet, DDR, JESD, and SERDES interfaces
Continuously improve test benches, simulation, and verification environments
Required Skills
Proficiency in Verilog/VHDL
Hands-on experience with Vivado or Quartus
Expertise in Static Timing Analysis (STA), floorplanning, and timing closure
Strong digital design and analytical skills
Knowledge of Signal Processing and Radar Digital Signal Processing
Experience balancing Area, Power, and Speed trade-offs
System-level debugging using Tcl scripting and logic analyzers
Preferred candidate profile
Requirements Generation, RTL design using VHDL, Good knowledge in DO-254 lifecycle. Good exposure to synthesis, timing analysis and design constraints, FPGA architecture: Vilinx/Altera, Exposure to PCIe, Arinc protocols etc., Continuously improve test and simulation environment.
Position Specific Requirements Proficiency in Verilog/VHDL, experience with Vivado or Quartus, and expertise in timing closure and high-speed protocols. Good in Digital and analytical skill. Good in Signal processing Position Specific Skills Proficiency in PCIe/Ethernet protocols and Multi-Gigabit Transceivers (SERDES). Worked in the areas like High speed interface like PCIe, DDR, JESD & Ethernet. Expertise in Static Timing Analysis (STA), floorplanning, and timing closure. Balancing architectural trade-offs between Area, Power, and Speed performance. System-level troubleshooting using Tcl scripting and logic analyzers. Expertise in RADAR Digital Signal Processing.
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Sneha Rajesh Solopreneur | Fortune Consultancy
📌 Senior Engineer HDD (Chennai)
🏢 Fortune Consultancy
📍 Chennai