Job Description Lead Verification Engineer
n Experience: 7+ years
n Location: Hyderabad
n Job Description:
n n Work as a member of a geographically distributed verification team to verify next-generation ASIC and FPGAs
n Develop testplans, implement testbenches, create testcases, and ensure functional coverage closure
n Handle regression testing and contribute to verification infrastructure development
n Develop both directed and random verification tests
n Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and test issues
n Review functional and code coverage metrics, modify or add tests or constrain random tests to meet coverage requirement
n Collaborate with design, software and architecture teams to verify design under test
n n Preferred Experience:
n n Proficient in IP-level FPGA and ASIC verification
n Knowledge of PCIe, CXL or other IO protocol is preferred
n Proficient in Verilog/SystemVerilog,



and scripting languages such as Perl or Python
n Hands-on experience with SystemVerilog and UVM is mandatory
n Experience in developing UVM-based verification testbenches, processes, and flows
n Solid understanding of design flow, verification methodology, and general computational logic design and verification
n n About Company
n ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

📌 Verification Lead (Hyderabad)
🏢 ACL Digital
📍 Hyderabad