Job Title: VLSI Physical Design Trainee (Education, R&D; & Innovation Projects)Job Overview

Job Overview:

We are seeking a motivated and enthusiastic VLSI Physical Design Trainee to work on Education-based projects (B.Tech, M.Tech, and Ph.D. level) along with Research & Development (R&D;) initiatives and real-time VLSI design projects.

The ideal candidate will contribute to Physical Design implementation, academic and research-driven projects, technical training sessions, project demonstrations, and innovation showcases. This role provides excellent exposure to the complete ASIC Physical Design flow, advanced semiconductor technologies, mentoring, and real-time industry projects.

Work Location: Tirupati

Key Responsibilities

- Work on Education-based projects (B.Tech / M.Tech / Ph.D. level) related to VLSI Physical Design.
- Assist in Research & Development (R&D;) and innovation-based semiconductor projects.
- Understand and implement the complete ASIC Physical Design (Place & Route) flow.
- Perform Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, Physical Verification, and Sign-off activities.
- Analyze and resolve timing, congestion, DRC, LVS, IR Drop, and power-related issues.
- Collaborate with RTL Design, Verification, and STA teams during the design cycle.
- Support project development, documentation, and technical reviews.
- Deliver technical presentations, project demonstrations, and knowledge-sharing sessions.
- Conduct technical training programs and workshops for students and junior engineers.
- Mentor students on academic projects and Physical Design concepts.
- Participate in technology expos, innovation showcases, and technical seminars.
- Stay updated with the latest semiconductor technologies,



EDA tools, and Physical Design methodologies.

Current Requirement:

We are expanding into the Physical Design domain and are looking for candidates who meet the following criteria:

- Strong understanding of the complete Physical Design (PNR) Flow, including:
- Floorplanning
- Placement
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- Physical Verification
- Sign-off
- Ability to effectively teach and mentor students in Physical Design concepts.
- Willingness to learn and collaborate with the RTL Design and Verification teams.
- Strong technical fundamentals with the ability to quickly learn new technologies and adapt to evolving project requirements.
- Excellent communication, presentation, mentoring, and interpersonal skills.
- Passion for innovation, continuous learning, and contributing to both project execution and technical training.

Required Skills & Expertise VLSI Physical Design

Strong proficiency in:

- ASIC Physical Design Flow
- Place & Route (PNR)
- Floorplanning
- Standard Cell Placement
- Clock Tree Synthesis (CTS)
- Routing
- Timing Closure
- ECO Implementation
- Physical Verification
- Sign-off Methodology

Timing Analysis

Experience with:

- Static Timing Analysis (STA)
- Setup & Hold Analysis
- Timing Optimization
- Crosstalk Analysis
- Signal Integrity
- RC Extraction

Physical Verification





Knowledge of:

- DRC
- LVS
- ERC
- Antenna Checks
- IR Drop Analysis
- EM Analysis

EDA Tools

Hands-on experience with tools such as:

- Cadence Innovus
- Synopsys ICC2
- PrimeTime
- Tempus
- Calibre
- Virtuoso (Basic Knowledge Preferred)

Scripting

Knowledge of:

- TCL
- Shell Scripting
- Python (Preferred)

Development & Collaboration

Experience with:

- Linux Setting
- Git & GitHub
- Documentation Standards

Soft Skills

- Strong analytical and problem-solving skills.
- Excellent communication and presentation skills.
- Ability to conduct technical training sessions and workshops.
- Strong mentoring and leadership abilities.
- Ability to work independently and collaboratively.
- Passion for semiconductor technology, research, and continuous learning.

Educational Qualifications:

B.E./B.Tech / M.Tech in:

- Electronics & Communication Engineering (ECE)
- Electrical & Electronics Engineering (EEE)
- VLSI Design
- Microelectronics
- Electronics Engineering
- Or related disciplines

Preferred Qualifications:

- Knowledge of complete ASIC Physical Design flow.
- Exposure to real-time semiconductor or VLSI projects.
- Experience with Cadence or Synopsys Physical Design tools.
- Participation in VLSI workshops, hackathons, research projects, or innovation programs.
- Experience in technical training, mentoring, or conducting workshops.
- Knowledge of RTL Design, STA, Verification, and Semiconductor Manufacturing concepts will be an added advantage.

How to Apply

Interested candidates can send their resumes to:

Email: [email protected]

Contact No.: (phone hidden)

Pay: From ₹15,000.00 per month

Work Location: In person

📌 VLSI Physical Design Trainee (Tirhe)
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