12 Aug
|
MosChip®
|
Vasanth Nagar
12 Aug
MosChip®
Vasanth Nagar
Job Description:Role: Senior RTL Design EngineerExperience: 6 - 12 Years of ExperienceLocation: Bangalore/ HyderabadWork Mode: Work from officeRequired SkillsExperience in Logic design / RTL coding is a must.Experience is SoC design and integration for complex SoCs is a must.Experience in Verilog/System-Verilog is a must.Experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint and CDC.Experience in Synthesis / Understanding of timing concepts is a plus.Experience in ECO fixes and formal verification.Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.Excellent oral and written communications skills.Proactive, creative, curious, motivated to learn and contribute with positive collaboration skills
📌 Senior RTL Design Engineer (Vasanth Nagar)
🏢 MosChip®
📍 Vasanth Nagar