12 Aug
|
L&T Technology Services
|
Vasanth Nagar
12 Aug
L&T Technology Services
Vasanth Nagar
Below is the JD for RTL engineers. We need to build robust RTL team.Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FVExperience in Logic design/micro-architecture/RTL coding is a must.Must have hands on experience with design and integration of complex multi clock domain blocksExperience in Verilog/System-Verilog is a must.Should have knowledge of AMBA protocols - AXI, AHB, APB, clocking/reset/debug architectureHands on experience in Multi Clock designs, Asynchronous interface is a must.Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.Work closely with the Design verification and validation teams for pre/post Silicon debugHands on experience in Low power design is preferableExperience in Synthesis / Understanding of timing concepts for ASIC is must
📌 RTL Design Lead (Vasanth Nagar)
🏢 L&T Technology Services
📍 Vasanth Nagar