? Hiring: STA Engineer | 5+ Years ? Location: Bengaluru

? Experience: 5+ Years

⏳ Notice Period: 0–30 Days

? Education: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines :

We are looking for an experienced Static Timing Analysis (STA) Engineer with strong expertise in block-level and full-chip timing analysis, timing closure, constraint development, and sign-off. Key Responsibilities:

Perform Block-Level and Full-Chip Static Timing Analysis.

Develop, validate and debug SDC timing constraints.

Analyze Setup, Hold, Recovery and Removal violations.

Drive timing closure across multiple design scenarios.

Perform MCMM timing analysis across PVT corners.

Debug timing violations and identify root causes.

Work closely with Physical Design, Synthesis, RTL and DFT teams for timing closure.

Analyze and resolve clock-related timing issues.

Support timing ECOs and implementation changes.

Perform timing sign-off and generate detailed timing reports.

Analyze OCV, AOCV, POCV and derating effects.





Work on Signal Integrity / Crosstalk-aware timing analysis.

Support timing closure for high-performance and complex SoC designs.

Required

Skills

Strong hands-on experience with Synopsys PrimeTime / Cadence Tempus.

Excellent knowledge of STA concepts and timing methodology.

Strong understanding of SDC constraints.

Good knowledge of MCMM, OCV, AOCV and POCV.

Strong understanding of clock architecture and clock timing.

Experience in timing ECO and closure methodologies.

Positive understanding of ASIC Physical Design flow.

Strong Tcl scripting skills.

Python knowledge is an added advantage. Preferred:

Experience in full-chip STA and sign-off.

Experience with advanced technology nodes.

Exposure to Signal Integrity, Crosstalk and Low-Power designs.

Experience working with large and complex SoC designs.

📌 STA Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru