12 Aug
|
ACL Digital
|
Bengaluru
12 Aug
ACL Digital
Bengaluru
Job DescriptionExperience: 4 to 12 Years.
NLocation: Bangalore.
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- Must have hands-on experience coding in System Verilog/UVM.
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- Experience developing testbenches for block level or IP level verification.
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- Experience working on subsystem or SoC level would be helpful.
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- Candidates should be proactive in communication and be able to work independently to self-manage the deliverable as per the schedules.
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- Developing and maintaining block level test benches.
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- Vplan, regression and coverage closure.
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- Work on testbenches with real number modeling.
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- Netlist and Gate level simulations.
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nNotice Period: 30 to 90 days
📌 Sr./ Lead Design Verification (Bengaluru)
🏢 ACL Digital
📍 Bengaluru