12 Aug
|
Source right
|
Hyderabad
12 Aug
Source right
Hyderabad
Position: Senior Design Veriifcation Engineer (IRT70ST RM 4305)
- Manage SOC Design Verification efforts for complex projects, ensuring the successful execution of verification plans.
- Develop and implement comprehensive verification strategies, test plans, and test benches for high-speed SOCs, including low-speed peripherals like I2C/I3C, SPI, UART, GPIO, QSPI, and high-speed protocols like PCIe, Ethernet, CXL, MIPI, DDR and HBM
- Experience on Gate-level simulations, and power-aware verification using Xprop and UPF is an added advantage
- Analyze and implement System Verilog assertions and coverage (code, toggle, functional).
- Demonstrate dedication, hard work, and commitment to achieving project goals and deadlines.
- Experience with verification tools from Synopsys and Cadence, including VCS and Xsim. Integration of third-party VIPs (Verification IP) from Synopsys and Cadence.
📌 Senior Design Veriifcation EngineerST RM 4305) (Hyderabad)
🏢 Source right
📍 Hyderabad