At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

This is an opportunity to contribute and innovate in the design of next-generation Memory subsystem Design IPs at Cadence. These advanced technology node IPs will enable the futuristic SoCs for Datacenter, Edge computing, Automotive and AI applications.

As a core member of the PHY Design team, your responsibilities will span across various aspects for the ASIC frontend flow, which includes developing micro-architecture/design specifications, implementing RTL code for complex digital logics, RTL integration, synthesizing and optimizing the design for better timing, PPA, doing performance analysis, setting up block level test bench, collaborating with the verification team and analyzing the coverage results. You will also be responsible for interfacing with the Physical Design team on STA, timing closure and P&R;, and participating in silicon bring up with the validation team. You will be working and interacting with accomplished digital and analog circuit designers.

You will work in a agile, team environment and must be an effective team player on projects. You will have ample opportunities to expand your knowledge, expertise and skillset. You would also be contributing to futuristic clocking architecture, design micro-architecture and RTL design decisions targeted at better timing, PPA, based on pre and post implementation timing analysis.

This is an opportunity to work and interact with accomplished digital and analog circuit designers and timing experts who has built industry leading multi protocol memory PHYs for over a decade.

Required Experience & Qualifications





BSEE and at least 7 years of prior experience required. MSEE and at-lest 5 years of prior experience strongly preferred.

Prior experience in timing and or RTL design of high-speed interfaces.

Prior experience of collaborating with Physical Design teams in multiple successful ASIC/IP tapeouts.

Knowledge of the IP/SoC level timing closure flow and methodology.

Strong command of Verilog/System Verilog language

Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies

Ability to handle multiple projects/tasks successfully

Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow

Hands on experience in timing constraints generation and management

Proficiency in scripting languages (TCL and Perl)

Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools

Capability to understand and implement improvements to existing methodologies and flows.

Strong background in Constraint analysis and debug, using industry standard tools.

Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, atspeed and Bist testing.

Team player with a passion to innovate and can-do attitude.

Self-starter and highly motivated.

Desired Skills

Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs

Experience designing or integrating IP

Experience in high speed and low power digital design using advanced deep micron process.

Experience with highly configurable designs

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📌 RTL Principal Design Engineer (DDR) (Bengaluru)
🏢 Cadence
📍 Bengaluru