(www.enchargeai.com)

Principal Engineer, Static Timing Analysis (STA)

Location: Greater Bengaluru Area (Hybrid)

About Company

:EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications.

EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems

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Role: Principal Engineer, Static Timing Analysis (ST

A)We are looking for a visionar y Principal Engine er to spearhead Encharge AI Timing leadership rol e.This isn't just an execution role; we need a technical trailblazer who can navigate the complexities of advanced process nodes (2nm/3nm and beyond) while fostering a culture of innovation and rigorous critical thinkin g.As the India Timing Lead, you will bridge the gap between architectural intent and silicon reality, ensuring our high-performance designs meet the most stringent timing, power, and reliability target s.Key Responsibiliti

- esTechnical Leadershi p: Drive the STA strategy for complex SoC and IP desig
- nsInnovation & Methodolog y: Develop and deploy "out-of-the-box" solutions for timing closure.

This includes defining sign-off margins, variation modeling (POCV/LVF), and managing multi-corner multi-mode (MCMM) scenario

- s.Execution Excellenc e: Lead the team through full-cycle STA, from initial constraints validation to final GDS sign-of
- f.Cadence Tempus Exper t:



Act as the primary subject matter expert fo r Cadence Temp us, optimizing tool flows for distributed processing, ECO generation, and power-aware timing analysi
- s.Cross-Functional Collaboratio n: Partner with RTL, Synthesis, and Physical Design teams to influence floorplanning and clock tree synthesis (CTS) strategies for timing-friendly layout
- s.Mentorshi
p: Elevate the technical caliber of the India team through active code reviews, white-boarding sessions, and fostering a "first-principles" approach to problem-solvin

g.Required Skills & Experti seCatego ryRequiremen tsCore S TADeep expertise i n Signal Integrity (S

I), Crosstalk, OCV/POCV/LVF, and Constraint Management (SDC

).Tooli ngMastery o f Cadence Temp us (ECO, Tempus Stylus, and distributed timing

).Analys isProficiency in high-speed interface timing (DDR, PCIe) and low-power multi-voltage domain s.Scripti ngAdvance d Tcl/Pyth on skills to automate complex flows and develop custom analysis tool s.Problem Solvi ngProven ability to debug complex timing paths and offer creative ECO solutions that balance Power, Performance, and Area (PPA

).Mindset & Qualificatio

- nsCritical Thinke r: You don't just follow a checklist; you challenge existing flows to find efficiencies and hidden risk
- s.Leadership Presenc

e: 14+ years of experience in VLSI, with a explicit track record of leading high-impact teams in Indi

- a.Educatio n: B.Tech/M.Tech in Electrical/Electronic Engineering or a related fiel

- d.Communicatio n: Ability to distill complex technical hurdles into actionable insights for global stakeholder

s.Skil lsE

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Udaymuday_bhaskar@yahoo

.comMulya Technolo gies"Mining the Knowledge Commun ity"

📌 Principal Engineer, Static Timing Analysis (STA) (Bangalore Metropolitan Area)
🏢 EnCharge AI
📍 Bangalore Metropolitan Area