? Hiring: Physical Design Engineer | 5+ Years ? Location: Bengaluru

? Experience: 5+ Years

⏳ Notice Period: 0–30 Days

? Education: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines :

We are looking for an experienced Physical Design Engineer with strong expertise in the complete RTL-to-GDSII implementation flow. The candidate will be responsible for physical implementation, timing closure, PPA optimization, and sign-off activities. Key Responsibilities:

Own and execute the complete Physical Design flow from netlist to GDSII.

Perform Floorplanning, Power Planning, Placement, CTS, Routing and Physical Verification.

Analyze and resolve timing, congestion, DRC and LVS issues.

Perform Setup/Hold timing analysis and timing closure.

Work on PPA optimization across different implementation stages.

Debug and resolve placement, routing, clock and signal integrity issues.

Work closely with STA, Synthesis, RTL, DFT and Verification teams.

Support ECO implementation and timing closure.





Perform physical design sign-off activities including DRC, LVS, Antenna and connectivity checks.

Work with advanced technology nodes and complex SoC designs.

Required

Skills

Robust understanding of ASIC Physical Design flow.

Hands-on experience with Innovus / ICC2 / Fusion Compiler or equivalent tools.

Good knowledge of Floorplanning, Placement, CTS and Routing.

Strong understanding of STA, SDC and timing constraints.

Experience in MCMM, OCV/AOCV/POCV.

Knowledge of IR Drop, EM and Signal Integrity is an added advantage.

Strong Tcl scripting skills; Python knowledge is a plus.

Good debugging, analytical and problem-solving skills. Preferred:

Experience in advanced nodes and full-chip implementation.

Experience with low-power designs and multi-voltage domains.

Exposure to EMIR, Physical Verification and sign-off flows.

📌 Physical Design Engineer (Bengaluru)
🏢 Leadsoc Technologies
📍 Bengaluru