Job Title: Design Verification Engineer PCIe Gen5/Gen6

Location: Bangalore

Experience: 5+ Years

Job Summary

We are looking for experienced Design Verification Engineers with solid expertise in PCIe Gen5/Gen6 protocol verification. The ideal candidate should have hands-on experience in developing verification environments, creating test plans, debugging complex designs, and working with industry-standard verification methodologies.

Key Responsibilities
Develop and execute verification plans for PCIe Gen5/Gen6 IP/SoCs.
Build reusable UVM/SystemVerilog verification environments.
Write and execute directed and constrained-random test cases.
Develop functional coverage and assertions.
Perform protocol compliance and corner-case verification.
Debug RTL issues and collaborate with Design and Architecture teams.




Analyze simulation results and improve verification quality.

Required Skills
5+ years of Design Verification experience.
Robust expertise in PCIe Gen5/Gen6 Protocol.
Excellent knowledge of SystemVerilog and UVM.
Experience with assertions (SVA).
Strong debugging and protocol analysis skills.
Experience in IP/SoC Verification.
Valuable understanding of verification methodologies.

Preferred Skills
Experience with C/C++.
Knowledge of scripting (Python/Perl/TCL).
Experience with protocol analyzers.
Exposure to high-speed interfaces (USB, DDR, Ethernet, CXL) is an advantage.

📌 Design Verification Engineer Pcie / Bengaluru
🏢 Kairos Technologies
📍 Bengaluru