Principal Engineer, Asic Physical Design Bengaluru

Principal Engineer, Asic Physical Design Bengaluru

11 Aug
|
Ayar Labs
|
Bengaluru

11 Aug

Ayar Labs

Bengaluru

Principal, ASIC Physical Design

Location: Bangalore (in office, adaptable schedule)

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next-generation AI scale-up architectures.

The ASIC Physical Design Engineer is responsible for the physical design and integration of complex SoCs with custom circuits, digital circuits, and photonics components as part of a high-speed electro-optical engine. The position focuses on the synthesis, place and route, timing closure, and physical verification steps of the design implementation process.





This PD Engineer is expected to take on full end-to-end responsibility for the implementation of complex blocks integrating both high-speed digital and custom blocks in leading edge process nodes.

Key Responsibilities:
Physical design of blocks containing digital and custom analog / mixed-signal blocks
Contribute to design for test (DFT) methodologies
Contribute to automated design methodologies for ASIC physical design
Perform ASIC physical design (synthesis, place-and-route), static timing analysis (STA), and physical verification (DRC/LVS) of mixed-signal SoCs
Coordinate and drive activities across multiple designers
Contribute across a broad range of CAD methodologies to improve design implementation flows

Basic Qualifications:
BS or MS in Electrical Engineering, Computer Engineering, or related fields
12+ years of work experience in ASIC physical design
History of leading successful block implementations integrating custom IP in leading edge process nodes
Proficient in Verilog RTL
Mastery of ASIC

📌 Principal Engineer, Asic Physical Design Bengaluru
🏢 Ayar Labs
📍 Bengaluru

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