Job Title: Synthesis Engineer

Experience: 5+ Years

Location: Bengaluru

Notice Period: Immediate to 30 Days Preferred

We are seeking an experienced Synthesis Engineer with 5+ years of expertise in RTL-to-Gate synthesis, timing closure, and logical equivalence checking for complex SoC designs. The ideal candidate should have hands-on experience with advanced technology nodes and solid collaboration with RTL, DFT, STA, and Physical Design teams.

Key Responsibilities
Perform RTL-to-Gate synthesis for block-level and full-chip designs.
Develop and maintain synthesis constraints (SDC).
Optimize designs for Power, Performance, and Area (PPA).
Perform timing, area, and power optimization to achieve synthesis closure.
Debug and resolve setup/hold timing issues and multi-clock domain challenges.
Work closely with STA and Physical Design teams to ensure smooth handoff and timing convergence.
Perform Formal Equivalence Verification (LEC) between RTL and synthesized netlist.
Support low-power synthesis using UPF/CPF methodologies.




Analyze synthesis reports and implement ECOs as required.

Required Skills
Solid knowledge of RTL-to-Gate synthesis flow.
Hands-on experience in:
RTL Synthesis
SDC Constraint Development
Timing Closure
Multi-Mode Multi-Corner (MMMC) Analysis
Clock Gating and Optimization
Logical Equivalence Checking (LEC)
Multi-Clock Domain Debugging
Low-Power Synthesis (UPF/CPF)
PPA Optimization

EDA Tools
Synopsys Design Compiler (DC)
Cadence Genus
Fusion Compiler
Synopsys Formality / Cadence Conformal
PrimeTime

Scripting Skills
TCL (Mandatory)
Perl/Python/Shell Scripting (Preferred)

Preferred Qualifications
Bachelor's or Master's degree in Electronics, ECE, VLSI, or a related field.
Experience with advanced technology nodes (16nm/7nm/5nm/3nm).
Solid debugging, analytical, and problem-solving skills.
Excellent communication and cross-functional collaboration skills.

📌 Synthesis Engineer Bengaluru
🏢 leadsoc technologies
📍 Bengaluru