Design Verification Engineer (Hyderabad)

Design Verification Engineer (Hyderabad)

12 Aug
|
ACL Digital
|
Hyderabad

12 Aug

ACL Digital

Hyderabad

Experience: 1-3 Years

Location: Hyderabad

Education: B.E./B.Tech. in ECE/EEE Roles and Responsibilities Robust expertise in UVM-based verification.

Hands-on IP-level verification exposure and a solid understanding of serial protocols are a must. Share resumes at [email protected]

📌 Design Verification Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad

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