Role Description The ideal candidate will have solid expertise in ASIC/SoC physical design flows, including synthesis, floorplanning, placement,PNR, clock tree synthesis, routing, timing closure, and sign-off. This role requires hands-on experience with industry-standard EDA tools and a deep understanding of advanced technology nodes. Key ResponsibilitiesExecute floorplanning, placement, CTS, routing, and timing closure.

Drive power, performance, and area (PPA) optimization. Conduct physical verification (DRC/LVS) and sign-off checks.Work on multi-voltage, low-power design techniques and UPF/CPF flows. Support ECO implementation and tape-out activities.

Required Skills & Qualifications 3-5 years of experience in ASIC/SoC physical design. Strong knowledge of EDA tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, PrimeTime, Voltus, etc.). Expertise in timing analysis, signal integrity, and power analysis.

Experience with advanced nodes (e.g., 16nm, 5nm).



Familiarity with DFT insertion, low-power design, and multi-clock domain handling. Good understanding of physical verification and manufacturing sign-off. Strong problem-solving and debugging skills.

Experience in working on Automotive or Industrial MPU/MCU SoCs (preferred for safety-critical designs and compliance with standards like ISO 26262).

Preferred Qualifications Experience with high-performance SoCs or complex IP blocks. Knowledge of EM/IR analysis and reliability checks. Familiarity with scripting languages (Tcl, Perl, Python) for flow automation.

Education Bachelor s or Master s degree in Electrical Engineering, Electronics, or related field.

Skills vlsi design,physical design,low power design,floor planning,electrical engineering

📌 Associate II - VLSI - PD SVP (Bengaluru)
🏢 UST
📍 Bengaluru