- Master’s with 1 year experience or Bachelor’s with 6 years experience
- Developing Assertion Based Verification packages and tools
- Assertion test plans for the various protocols
- Full chip verification using Verilog, C, Object Oriented Programming
- Silicon/Board debug
- Working with PCIE, PSL, System Verilog, OVL, Verilog, PERL, NCVerilog and Modelsim
Email your resume to [email protected] with Job Code
- - DVE in the subject line