Job DescriptionJob Summary:
nWe are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits.
nResponsibilities
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- :Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verificationn
- )Design and create high-quality verification environments (testbenches) to achieve exceptional code coveragn
- eUtilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionalitn
- yDebug and analyze verification failures with a keen eye to identify and resolve the root cause of design issuen
- sCollaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherencn
- eLead and mentor junior DV engineers within the team, fostering a cooperative and knowledge-sharing environmenn
- tParticipate in code reviews and champion best practices for verification code qualitn
- yStay current with the latest advancements in verification tools and methodologien
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n Qualification
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- s:Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plun
- s)7-10 years of solid experience in Design Verification for ASICs or Son
- CsIn-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machinen
- s)Proven ability to develop, debug, and optimize complex verification environmenn
- tsExpertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Forman
- l)Extensive experience with simulation tools (ModelSim, Cadenc