Job DescriptionWe are seeking an experienced, highly motivated and high-caliber individual with below expertise. Does this sound like a positive role for you?
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- Sr Staff RTL Design Engineer (R&D; engineering)n
- Location: Bengalurun
- Experience: 9yrs to 15yrsn
- BSEE with 9 years of relevant experience OR MSEE with 8 years of relevant experience.n
- Expertise in RTL development using Verilog or System Verilog, with a strong background in digital design principles.n
- Hands-on experience with Xilinx and Altera FPGA platforms, including familiarity with Xilinx Vivado and related tools.n
- Proficiency in developing large, complex EDA software and managing the full design flow from concept to lab bring-up.n
- Advanced problem-solving and debugging skills, especially in digital verification, emulation, and prototyping environments.n
- Experience with scripting languages such as Tcl, Python, Perl, and a solid understanding of system and CPU architecture (DMA, interrupts, etc.).n
- Exposure to embedded system development and interface protocols (USB, PCIe, DDR, AXI).n




- Responsibilities:n
- Designing and developing advanced FPGA-based prototyping solutions, integrating both hardware and software components.n
- Leading the digital design process for Xilinx and Altera FPGAs, utilizing tools such as Xilinx Vivado to optimize workflows.n
- Driving all phases of the project lifecycle, including requirements gathering, development, implementation, and test case creation.n
- Developing and maintaining complex EDA (Electronic Design Automation) software for high-performance prototyping systems.n
- Implementing digital debug, verification, emulation, and prototyping strategies to ensure robust and reliable designs.n
- Creating RTL for interfaces such as USB, PCIe, DDR, and AXI, and overseeing full design flow including verification and lab bring-up.n
- Exploring and implementing new approaches to address current and future challenges, continuously learning and

📌 Senior RTL Design Engineer (Karnataka)
🏢 Synopsys
📍 Karnataka